Synthesis of a parallel data stream processor from data flow process networks

Leiden Repository

Synthesis of a parallel data stream processor from data flow process networks

Type: Doctoral Thesis
Title: Synthesis of a parallel data stream processor from data flow process networks
Author: Zissulescu-Ianculescu, Claudiu
Publisher: LIACS Embedded Research Center (LERC), Leiden Institute of Advanced Computer Science (LIACS), Faculty of Science, Leiden University
Issue Date: 2008-11-13
Keywords: KPN
Compaan
Laura
Synthesis
VHDL
Polytope
Abstract: In this talk, we address the problem of synthesizing Process Network specifications to FPGA execution platforms. The process networks we consider are special cases of Kahn Process Networks. We call them COMPAAN Data Flow Process Networks (CDFPN) because they are provided by a translator called the COMPAAN compiler that automatically translates affine nested loop programs to input-output equivalent (COMPAAN) process network specifications. The objective is to provide an effective and efficient implementation of CDFPNs in an FPGA execution platform, where our implementation is close to a one-to-one mapping of the originating CDFPN. The execution platform emerges as part of the mapping process resulting in a dedicated multi-processor execution platform for a given CDFPN specification.
Description: Promotor: E.F.A. Deprettere, Co-promotor: A.C.J. Kienhuis
With Summary in Dutch
Faculty: Faculteit der Wiskunde en Natuurwetenschappen
Citation: Zissulescu-Ianculescu, C., 2008, Doctoral Thesis, Leiden University
Sponsor: LIACS
Handle: http://hdl.handle.net/1887/13262
 

Files in this item

Description Size View
application/pdf Full text 691.2Kb View/Open
application/pdf Propositions 38.14Kb View/Open

This item appears in the following Collection(s)